1. Field of Invention
This invention relates to a method for arranging EEPROM (Electrically Erasable Programmable Read Only Memory) cells and a semiconductor device manufactured by the method, and more particularly to a method for arranging EEPROM cells such that if a bit line is selected, a bit line adjacent to the bit line becomes a ground line without forming an additional ground line during the cell arrangement and it is connected to the bit line by selecting the predetermined buried diffusion region by a selecting transistor in order to connect the selected bit line to a buried diffusion region separated into a plurality of segments.
2. Information Disclosure Statement
In the prior art, the EEPROM cell arrangement structure requires a ground line and two bit lines for two cells in the bit line direction and, the contact region is needed at the bit line. This arrangement structure presents a problem in that the area of cell is increased in the EEPROM cell arrangement due to the contact for the bit line, and the distance between the contact and the poly layer for gate electrode. Accordingly, in order to solve the problem with the prior art arrangement structure, an attempt had been made to decrease the number of the contacts by forming the buried diffusion region in the substrate in the EPROM cell arrangement.
However, greater parasitic capacitance is produced between the substrate and the diffusion region due to successive formation of the buried diffusion regions under the predetermined cell which is connected to a bit line, thereby resulting in the increase of the time for precharging and discharging the buried diffusion region coupled to the bit line.